In conventional semiconductor integrated circuit processing, various front-side annealing techniques, such as rapid thermal processing (RTP), flash lamp (FL) and laser spike annealing (LSA), are commonly utilized to activate dopants and remove defects for ultra-shallow ion-implanted junctions. During performance of these annealing processes, temperature variations occur at different points or areas within the integrated circuit die. Temperature variations within a die are due primarily to differences in thermal absorption and emission caused by different film stacks at different locations. Various publications have shown that different materials on the front-side give rise to emissivity variations that can lead to significant local variations in temperature (e.g., incident light is absorbed/reflected differently depending on film composition).
At larger device dimensions, these temperature variations have little or no effect. However, as device dimensions shrink, the impact of these temperature variations has an increased effect on device performance by affecting electrical response. Variations in device performance within a die have been observed and are attributed to temperature non-uniformity when the wafer (and its dies) undergoes front-side annealing schemes. These temperature variations not only result from differences in film stack materials, but also result from the pattern density across the die. In addition, when annealing duration is reduced, diffusion lengths are similarly reduced which leads to increased temperature non-uniformity.
Accordingly, there is a need for an improved fabrication process (and resulting devices) that reduces temperature variations within an integrated circuit die and/or minimizes their impact on device performance.